U.S. Pat. No. 5,497,019 shows a dual-gate transistor in which the lower gate is formed by flip-bonding a second wafer to the wafer containing the main portion of the transistor.
Yang, et al (J. Vac. Sci. Tech., vol. B14, 4204 (1996) show a dual-gate SOI FET in which selective doping of an insulating polysilicon bottom gate results in the drawback of lateral diffusion of the dopant.
Colinge, et al show a dual-gate transistor with a cavity under the gate that is not self-aligned and therefore will result in greater capacitance.